Negative resistance field-effect element

ABSTRACT

A negative resistance field-effect element that is a negative differential resistance field-effect element capable of achieving negative resistance at a low power supply voltage (low drain voltage) and also enabling securement of a high PVCR is formed on its InP substrate  11  having an asymmetrical V-groove whose surface on one side is a (100) plane and surface on the other side is a (011) plane with an InAlAs barrier layer ( 12 ) that has a trench (TR) one of whose opposed lateral faces is a (111) A plane and the other of which is a (331) B plane. An InGaAs quantum wire ( 13 ) that has a relatively narrow energy band gap is formed at the trench bottom surface as a high-mobility channel. An InAlAs modulation-doped layer ( 20 ) having a relatively wide energy band gap is formed on the quantum wire as a low-mobility channel. A source electrode ( 42 ) and a drain electrode ( 43 ) each in electrical continuity with the quantum wire ( 13 ) constituting the high-mobility channel through a contact layer ( 30 ) and extending in the longitudinal direction of the quantum wire ( 13 ) as spaced from each other, and a gate electrode ( 41 ) provided between the source electrode ( 42 ) and the drain electrode ( 43 ) to face the low-mobility channel ( 20 ) through an insulating layer or a Schottky junction, are provided. Owing to the foregoing configuration, a very narrow-width quantum wire whose lateral confinement size can, without restriction by the lithographic technology limit, be made 100 nm or less is usable as a high-mobility channel, whereby there can be obtained a negative resistance field-effect element that develops a negative characteristic at a low power supply voltage and enables securement of a high PVCR.

TECHNICAL FIELD

The present invention relates to a field-effect element that exhibitsnegative differential resistance (NDR) and more particularly relates toan improvement for enhancing a peak-to-valley current ratio (hereinafterabbreviated as PVCR), which, being the ratio between drain current valueimmediately before negative differential resistance is exhibited anddrain current value immediately after occurrence of negativedifferential resistance, is an index for measuring negative differentialresistance effect, and, further, for enabling the field-effect elementto exhibit a negative characteristic at a low power supply voltage. Inthis description, a field-effect element that exhibits negativedifferential resistance will, in accordance with general practice, becalled simply a negative resistance field-effect element.

BACKGROUND ART

Elements having negative differential resistance are required insemiconductor integrated circuits. As with other active elements, such anegative resistance element of course becomes more attractive with theelement's ability to operate at lower voltage and operate at higherspeed (with better high-frequency characteristics) and, as such, hasbeen a subject of various studies in the past.

Although a so-called two-terminal element having no control terminalexists, the lack of a control terminal itself tends to be a drawback,limiting control from the outside and usually making the elementunsuitable for application as a logic element and as an integratedelement. Naturally, no amplification capability or the like can beanticipated. Therefore, a need is, after all, felt for a negativeresistance element having a three-terminal structure including at leasta control terminal. This assumes, however, what will no doubt continueto be most emphasized as a future trend will be realization oflow-voltage operation and a high PVCR.

One response to this has been the proposal of a configuration using acompound heterojunction structure utilizing a high-mobility layerportion whose energy band gap is relatively narrow as the main transitchannel for electrons and providing as a second channel in contact withthis a low-mobility layer portion with a relatively wide energy band gap(e.g., Reference 1: “Enhanced Resonant Tunneling Real-Space Transfer indelta-Doped GaAs/InGaAs Gated Dual-Channel Transistors Grown by MOCVD”,Chang-Luen Wu et al., IEEE Transactions on Electron Devices, vol. 43,No. 2 (1996) 207).

In such a low-dimensional field-effect element having a dual-channelstructure, transit electrons (hot carriers) accelerated by the drainvoltage and raised to the energy level of the potential barrier betweenthe two channels are real-space-transferred to the low-mobility channelsandwiched between the gate and the main high-mobility channel byapplying gate voltage positively. The electrons transferred to thelow-mobility channel travel at a reduced speed or stop. As a result, theplanar density of the electrons passing through the high-mobilitychannel becomes equal to the result of subtracting the chargeaccumulated in the low-mobility channel from the total amount of chargeinduced by the gate voltage for satisfying charge neutrality condition,thereby producing the same effect as biasing the gate bias by the sameamount in the negative direction. Therefore, owing to the resultingdecrease of electrons in the high-mobility channel, the drain currentdeclines substantially to give rise to negative differential resistance.

On the other hand, the present inventors previously proposed that forimplementing this principle a dual-channel field-effect elementstructure using a quantum wire for the high-mobility channel isadvantageous for suppressing dispersion of carriers in the channel (JP-A2001-185559). Negative resistance is easier to induce in this elementthan in one using a quantum well, making it promising for use as anultrahigh-speed logic element and the like.

However, it was difficult to actually make the lateral confinement sizeof the quantum wire smaller than around 100 nm and, therefore, while thepower supply voltage at which negative differential resistance appeared(generally the drain voltage of a field-effect element) could be loweredcompared with the prior art, it could still not be reduced adequately.Or to put it more exactly, there still was room for improvement.

An object of the present invention is to provide a negative resistancefield-effect element that can achieve negative resistance at a lowerdrain voltage than conventionally while also ensuring a PVCR of adequatevalue.

The negative resistance field-effect element according to the presentinvention comprises: an InAlAs or AlGaAs barrier layer that, owing tobeing formed on an InP or GaAs substrate having an asymmetrical V-groovewhose surface on one side is a (100) plane and surface on the other sideis a (011) plane, has a trench, one of whose opposed lateral faces is a(111) A plane and the other of which is a (331) B plane; an InGaAs orGaAs quantum wire grown on a trench bottom surface of this barrier layeras a high-mobility channel having a relatively narrow energy band gap;an InAlAs or AlGaAs spacer layer grown on this quantum wire as alow-mobility channel having a relatively wide energy band gap; a sourceelectrode and a drain electrode each in electrical continuity with thehigh-mobility channel through a contact layer and extending in alongitudinal direction of the quantum wire as spaced from each other;and a gate electrode provided between the source electrode and the drainelectrode to face the low-mobility channel through an insulating layeror a Schottky junction.

Further, the present invention encompasses an element in which adelta-doped layer that lowers conduction band energy is provided locallywithin the low-mobility channel and the InAlAs or AlGaAs spacer layerconstitutes a modulation-doped layer, and an element in which thecontact layer contacted by the source electrode and drain electrode is alaminated structure of an n-type InAlAs layer, an n-type InGaAs layer,an n-type InGaAs layer and an n-type InAs layer.

Owing to the foregoing structure, lateral confinement size can, withoutrestriction by the lithographic technology limit, be made 100 nm or lessif required to thereby enable use of a very narrow-width quantum wire asthe high-mobility channel and thereby achieve the object.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1(A) is a cross-sectional structural diagram of an embodiment ofthe negative resistance field-effect element according to the presentinvention.

FIG. 1(B) is a cross-sectional structural diagram in a directionperpendicular to the negative resistance field-effect element of FIG.1(A).

FIG. 2 is a static characteristic plot of drain-source voltage versusdrain current obtained at room temperature in an example of the negativeresistance field-effect element according to the present invention.

FIG. 3 is a static characteristic plot of drain-source voltage versusdrain current obtained at 40 K in an example of the negative resistancefield-effect element according to the present invention.

FIGS. 4(A), (B) and (C) are explanatory diagrams of an example of atrench shape for forming quantum wires that is advantageous for use infabricating a negative resistance field-effect element according to thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

A preferred embodiment of a negative resistance field-effect element 10configured according to the present invention is shown in FIGS. 1(A) and(B). As viewed statically from the sectional structure shown in theleft-side diagram of FIG. 1(A), an InAlAs or AlGaAs barrier layer, inthis case an InAlAs barrier layer 12, is formed on an InP or GaAssubstrate, in the illustrated case an InP substrate 11, having anasymmetrical V-groove, thereby forming a trench TR that is a deepV-groove having very steep lateral faces at the location of the InAlAsbarrier layer 12 where the V-groove is present in the underlying InPsubstrate 11. The distance between the inclined surfaces near the bottomportion of the trench TR (space width) can, as explained later, beformed very narrowly.

Details of the sectional lamination at the essential portion enclosed bythe phantom line in the left-side diagram are shown in the right-sidediagram of FIG. 1(A). Referring to this, first an InGaAs or GaAs quantumwire, in this case an InGaAs quantum wire 13, having a relatively narrowenergy band gap is formed on the bottom surface of the trench TR of theInAlAs barrier layer 12 as a high-mobility channel, and an InAlAs orAlGaAs spacer layer, in this case an InAlAs spacer layer 20, having arelatively wide energy band gap is formed on this as a low-mobilitychannel 20.

In this embodiment, however, the low-mobility channel 20 can actuallyalso be viewed as a two-layer structure of a lower layer 21 and an upperlayer 22. This is because, in order to utilize the forming of adepression in the conduction band of the low-mobility channel 20 so asto make it easy to capture carriers passing from the high-mobilitychannel through the tunnel barrier to arrive by real-space transfer, adelta-doped layer (δ-doped layer) 22 constituted of an n-type siliconsingle-atom layer is included midway of the depth thereof. From thedoping aspect, such a low-mobility channel 20 is also called amodulation-doped layer.

As explained later, on the low-mobility channel 20 is formed a contactlayer 30 for each of a source electrode 42 and a drain electrode 43. Thecontact layer 30 in this embodiment is a non-alloy contact layer alsoconstituted as a laminated structure of multiple layers, having ann-InAlAs layer 31, an n-InGaAs layer 32, a delta-doped layer 33, ann-InAlAs layer 34 and an n-InAs layer 35 stacked in this order startingfrom the bottom layer. While this is based on the conditions forachieving good mutual lattice matching, good conductivity and good ohmiccontact of the source electrode 42 and drain electrode 43, otherconsiderations are of course also conceivable and the number of stackedlayers and the material thereof are not restricted insofar as theforegoing object is achieved.

In FIG. 1(B) is shown the related cross-sectional structure lyingperpendicular to FIG. 1(A). The source electrode 42 and drain electrode43 are provided on the contact layer 30 in accordance with a knownexisting lithography technique to be in electrical continuity with thequantum wire 13 constituting the high-mobility channel and to extend inthe longitudinal direction of the quantum wire 13 as disposed in amutually spaced relationship. Further, between the source electrode andthe drain electrode is formed, preferably by the self-alignment method,a gate electrode 41 that faces the low-mobility channel 20 through aninsulating layer or a Schottky junction (in this case through a Schottkyjunction with respect to the modulation-doped layer 20). Generally,appropriate oxide layers, e.g., silicon dioxide layers 44, are formed onthe regions between the opposite sides of the gate electrode 41 and thesource and drain electrodes.

It should be noted that while in the case of the illustrated embodimentthe contact layer 30 is structured first to contact the low-mobilitychannel 20 and further to be in continuity with the quantum wire 13constituting the high-mobility channel through the low-mobility channel20, the contact layer 30 can be fabricated to directly contact thehigh-mobility channel 13. Although the electrode material is arbitrary,Ti/Pt/Au and the like can be cited by way of example.

In such element 10 of the present invention, upon application of a gatevoltage of appropriate magnitude, the carriers in the high-mobilitychannel 13 that have been accelerated by the drain voltage to become hotcarriers pass through the energy barrier between the high-mobilitychannel 13 and the low-mobility channel 20 to move into the low-mobilitychannel 20, where they travel or stop. Because of this, as was pointedout earlier, a situation arises that is substantially equivalent to thatof increasing the gate voltage in the negative direction, giving rise tonegative differential resistance that reduces the drain current.

To rephrase, owing to the charge neutrality condition, since the totalamount of electrons accumulated at a given gate voltage is fixed, theelectrons of the high-mobility channel 13 decrease by the amount ofelectrons transferred to the low-mobility channel 20 to lower theconductance there and give rise to negative differential resistance.Here, when, as in this embodiment, the delta-doped layer 22 is providedin the low-mobility channel 20, a depression whose deepest portion is atthe delta-doped layer occurs in the conduction band to ensure stablecapturing/stopping of the tunnel-transferred carriers. However, as amatter of operating principle, this delta-doped layer is not needed andit suffices for the aforesaid dual-channel structure to be satisfied.

Still, as mentioned earlier, one important key from the aspect of theelement's characteristics rests in how to obtain a narrow-width,fine-cross-section quantum wire 13 with a large quantum-confinementeffect. And in this regard, there can, at least in accordance with thelimiting conditions among the substantial constituents of the presentinvention, be obtained a quantum wire 13 that is at least narrower thanthat of the prior art without restriction by the lithographic technologylimit. However, regarding this, some of the inventors have in additionalready obtained very fine quantum wires in actual practice.

In the following, therefore, explanation will be given with respect to astill more concrete example of fabricating a negative resistancefield-effect element 10 of the present invention that includes a methodin accordance therewith. First, as shown in FIG. 4(A), a 2-μmline-and-space pattern is formed in the [01-1] direction on an InP (311)A substrate using an ordinary photolithography process and anasymmetrical V-groove is then produced by chemical etching (wet etching)using an HCl:H₃PO₄:H₂O₂ (=50:10:1) solution. The inclined surfaces ofthe asymmetrical V-groove are formed in the (100) plane and the (011)plane. The angle between the inclined surfaces is 90 degrees. After thesurface oxide film of this substrate is removed with hydrofluoric acid,the substrate is introduced into an MBE (molecular beam epitaxy) chamberand substrate surface cleaning is conducted by increasing the substratetemperature to 400° C. and holding it thereat for 2 minutes underexposure to atomic hydrogen.

When the InAlAs (or AlGaAs) barrier layer 12 is grown on the InP (311)A-V-groove substrate 11 by MBE while restraining dispersion of adsorbedatoms by a V-group source using cracking As₂, then, as shown in FIG.4(B) and the enlarged essential portion thereof in FIG. 4(C), a (111) Aplane is formed on the inclined lateral face of the (100) plane and a(331) B plane is formed on the lateral face of the (110) plane to formthe trench TR, namely, a sharp V-groove with an intersection angle of 22degrees. A deep trench TR of such steeply inclined surface configurationcannot be formed by another method of the prior art.

As was explained earlier, when an InGaAs or GaAs quantum wire is grownon the bottom of such a trench TR, a quantum wire 13 of very narrowwidth exceeding the lithography limit can be formed. As also explainedearlier, for this it suffices to successively form the low-mobilitychannel 20 and the contact layer 30 by an appropriate conventionalmethod.

By way of further information, the thickness of each of the differentlayer films in the inventors' prototype is: InAlAs barrier layer 12, 400nm; InGaAs quantum wire 13, 10 nm; InAlAs spacer layer 21, 10 nm; InAlASspacer layer 23, i.e., upper layer on other side of the delta-dopedlayer 22, 15 nm, n-InAlAs layer 31 and n-InGaAs layer 32 in non-alloyohmic contact layer 30, 1 nm and 5 nm; upper n-InAlAs layer 34 on otherside of delta-doped layer, 1 nm; and n-InAs layer, i.e., uppermostlayer, 1 nm. The In, Ga and Al fluxes are In_(0.53)Ga_(0.47)As andIn_(0.52)Al_(0.48)As, values at which the InGaAs and InAlAs compositionslattice-match on the InP substrate. Regarding the As partial pressureduring growth, As₄ is set at 1.3×10⁻³ Pa and As₂ at 8.3×10⁻⁴ Pa. As₄ isused for growth starting from the InGaAs quantum wire 13.

The static characteristics at room temperature of the negativeresistance field-effect element 10 according to the present inventionare shown first in FIG. 2. The horizontal axis represents thedrain-source voltage Vds and the vertical axis the drain current Id. Thesection of the quantum wire 13 is fabricated to about 10 nm×about 20 nmand the gate length to 2 μm. At room temperature, the characteristicsare those of an ordinary field-effect transistor (FET) having goodsaturation characteristics. In contrast, as shown in FIG. 3, when theoperating temperature is reduced to 40 K, pronounced negativedifferential resistance is observed. This is negative resistanceproduced by gate field-assisted real space transfer and is produced byelectrons of the InGaAs quantum wire 13 serving as the high-mobilitychannel passing through the tunnel barrier and tunneling into thelow-mobility channel 20. The drain voltage at which negative resistancearises (Onset Voltage: V_(NDR)) is 0.12 V when Vg=−0.1 V, which is verylow in comparison with negative resistance devices reported heretofore.As regards PVCR as well, an adequate value of 4.3 when Vg=−0.1 V issecured.

Although the drain voltage at which negative resistance develops fallstogether with the gate voltage from 0.2 V, this is because the effectivebarrier layer height as viewed from the channel decreased owing to thegate voltage. In the case of a conventional real-time transfer element,the voltage at which negative resistance appears is 1 V or greater, sothat the enhancement of element characteristics by the present inventionis marked.

It is noted that although the drain voltage at which negativedifferential resistance arises tends to decrease with increasing devicetemperature, this is thought to be because increase in carriertemperature causes a relative lowering of the height of the barrierlayer through which the carriers are to be transferred.

INDUSTRIAL APPLICABILITY

An explanation was made in the foregoing with reference to a preferredembodiment of the present invention. Since the negative resistancefield-effect element of the present invention can achieve negativeresistance at a low drain voltage and achieve an adequate PVCR, it hasmerits and features unavailable heretofore and, as such, can be expectedto find applications in low-power consumption high-frequency generators,memories and the like.

1. A negative resistance field-effect element comprising: an InAlAs orAlGaAs barrier layer (12) that, owing to being formed on an InP or GaAssubstrate (11) having an asymmetrical V-groove whose surface on one sideis a (100) plane and surface on the other side is a (011) plane, has atrench (TR), one of whose opposed lateral faces is a (111) A plane andthe other of which is a (331) B plane; an InGaAs or GaAs quantum wire(13) grown on a trench bottom surface of the barrier layer as ahigh-mobility channel having a relatively narrow energy band gap; anInAlAs or AlGaAs spacer layer (21) grown on the quantum wire as alow-mobility channel having a relatively wide energy band gap; a sourceelectrode (42) and a drain electrode (43) each in electrical continuitywith the high-mobility channel (13) through a contact layer (30) andextending in a longitudinal direction of the quantum wire as spaced fromeach other; and a gate electrode (41) provided between the sourceelectrode and the drain electrode to face the low-mobility channelthrough an insulating layer or a Schottky junction.
 2. The negativeresistance field-effect element according to claim 1, further comprisinga delta-doped layer (22) that lowers conduction band energy and isprovided locally within the low-mobility channel (20) and wherein theInAlAs or AlGaAs spacer layer constitutes a modulation-doped layer. 3.The negative resistance field-effect element according to claim 1,wherein the contact layer (30) is a laminated structure of an n-typeInAlAs layer (31), an n-type InGaAs layer (32), an n-type InAlAs layerand an n-type InAs layer.